In recent years, so-called thin display devices such as a liquid crystal display device have been widely applied to various equipments including mobile equipments such as a cellular phone, television monitors, and the like. An active matrix-type liquid crystal display device will be described below as an example. The liquid crystal display device has an active matrix substrate, a counter substrate positioned so as to face the active matrix substrate, and a liquid crystal layer sealed between these substrates.
A common electrode, a color electrode, and the like are formed on the counter substrate. The active matrix substrate, on the other hand, has a plurality of pixels arranged in a matrix pattern, and a thin film transistor (hereinafter referred to as the “TFT”) as a switching device is formed in each pixel. Thus, driving of each TFT is controlled to apply a driving voltage to the liquid crystal layer corresponding to each pixel, thereby providing desired display.
Incidentally, a TFT has a semiconductor layer, and a gate electrode provided on the semiconductor layer with a gate insulator interposed therebetween. The semiconductor layer includes a source region and a drain region which are formed as impurity regions by implanting p-type impurities or n-type impurities by using the gate electrode as a mask. A channel region formed between the source region and the drain region has been lightly doped with, for example, p-type impurities in order to adjust the threshold voltage.
For example, amorphous silicon, polysilicon, or the like can be used for the semiconductor layer. In the case where the semiconductor layer of the TFT is amorphous silicon, it is necessary to mount a driver IC on the active matrix substrate to drive the TFT due to relatively low carrier mobility of amorphous silicon. In the case where the semiconductor layer of the TFT is polysilicon, on the other hand, a drive circuit including that TFT can be directly fabricated on the active matrix substrate due to relatively high carrier mobility of polysilicon.
In order to reliably cover an outer edge portion of the semiconductor layer with the gate insulator, it is known to form a tilted portion on the outer edge portion, which is widened from the gate electrode in the thickness direction of the semiconductor layer.
However, the tilted portion formed in the semiconductor layer of an n-type TFT causes a problem of humped characteristics generated in a sub-threshold region of the current-voltage characteristics, as shown in FIG. 13 (see, e.g., Patent Document 1). In view of this problem, Patent Document 1 attempts to eliminate the humped characteristics by additionally doping the tilted portion of the semiconductor layer with impurities.
Patent Document 1: Japanese Published Patent Application No. 2002-343976